DS3106LN+【PDF 16/92 页】IC TIMING LINE CARD 64-LQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录1994

12页 13页 14页 15页 [16页]17页 18页 19页 20页

DS3106

7.7.1.7 Mini-Holdover

When the selected reference fails, the fast activity monitor (Section 7.5.3) isolates the T0 DPLL from the reference

within one or two clock cycles to avoid adverse effects on the DPLL frequency. When this fast isolation occurs, the

DPLL enters a temporary mini-holdover mode, with a frequency equal to an instantaneous value 50ms to 100 ms

old from the integral path of the loop filter. Mini-holdover lasts until the selected reference becomes active or the

state machine enters the holdover state. If the free-run holdover mode is set (FRUNHO = 1 in MCR3), the mini-

holdover frequency accuracy is exactly the same as the external oscillator accuracy plus the offset set by the

MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3).

7.7.2 Bandwidth

The bandwidth of the T0 DPLL is configured in the T0ABW and T0LBW registers for various values from 18Hz to

400Hz. The AUTOBW bit in the MCR9 register controls automatic bandwidth selection. When AUTOBW = 1, the

T0 DPLL uses the T0ABW bandwidth during acquisition (not phase-locked) and the T0LBW bandwidth when

phase-locked. When AUTOBW = 0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition

and when phase-locked.

When LIMINT = 1 in the MCR9 register, the DPLL’s integral path is limited (i.e., frozen) when the DPLL reaches

minimum or maximum frequency. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in.

7.7.3 Damping Factor

The damping factor for the T0 DPLL is configured in the DAMP field of the T0CR2 register. The reset default

damping factor is chosen to give a maximum jitter/wander gain peak of approximately 0.1dB. Available settings are

a function of DPLL bandwidth (configured in the T0ABW and T0LBW registers). See Table 7-4.

Table 7-4. Damping Factors and Peak Jitter/Wander Gain

BANDWIDTH

(Hz)

DAMP[2:0]

VALUE

DAMPING

FACTOR

GAIN PEAK

(dB)

1.2

0.4

2.5

0.2

3, 4, 5

0.1

1.2

0.4

2.5

0.2

0.1

4, 5

0.06

70 to 400

1.2

0.4

2.5

0.2

0.1

0.06

0.03

7.7.4 Phase Detectors

Phase detectors are used to compare a PLL’s feedback clock with its input clock. Several phase detectors are

available in the T0 DPLL:

Phase/frequency detector (PFD)

Early/late phase detector (PD2) for fine resolution

Multicycle phase detector (MCPD) for large input jitter tolerance and/or faster lock times

These detectors can be used in combination to give fine phase resolution combined with large jitter tolerance. As

with the rest of the DPLL logic, the phase detectors operate at input frequencies up to 77.76MHz. The multicycle

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式